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aCOSwt
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Joined: 19 Oct 2007
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 Posted: Tue Jul 13, 2010 5:23 pm Post subject: 2.6.34 x86_64/Where has the GART IOMMU support gone[Solved] |
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Well,... about everything in the title... 
Last edited by aCOSwt on Wed Jul 14, 2010 4:15 pm; edited 1 time in total |
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dmpogo
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| Posted: Tue Jul 13, 2010 7:11 pm Post subject: Re: 2.6.34 x86_64 / Where has the GART IOMMU support gone ? |
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| aCOSwt wrote: | | Well,... about everything in the title... |
Not answering your question - but do you need it ? I had it disabled for last 4 years |
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aCOSwt
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| Posted: Tue Jul 13, 2010 7:39 pm Post subject: |
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| Well, as a matter of fact, I do not know that I actually need it, I just suspect that I needed it on my 4GB Intel machine in order to enable full DMA with my old TurtleBeach sound system; |
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asturm
Developer
Joined: 05 Apr 2007
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| Posted: Tue Jul 13, 2010 8:52 pm Post subject: |
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Shouldn't have anything to do with sound, just graphics. 
GART
IOMMU |
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dmpogo
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| Posted: Tue Jul 13, 2010 9:03 pm Post subject: |
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| genstorm wrote: | Shouldn't have anything to do with sound, just graphics.
GART
IOMMU |
I don't think that's true, IOMMU was used for all kind of devices which are not able to address memory above 4Gb.
It is just that one of its implementation (GART IOMMU) is using memory window reserved for AGP.
That is GART is for graphics, but GART IOMMU is not, it just uses resources usually reserved for graphics.
At the same time, I never encountered devices that actually need IOMMU, and remained unclear on its use.
Quote from this discussion of AMD IOMMU http://developer.amd.com/documentation/articles/pages/892006101.aspx
| Quote: |
What's an IOMMU?
An IOMMU manages device access to system memory. It sits between peripheral devices and the host, translating addresses from device requests into system memory addresses and checking appropriate permissions on each access.
Typically, AMD's IOMMU will be deployed as part of a HyperTransport or PCI bridge device. In high-end systems where there may be multiple HyperTransport links between CPU(s) and I/O hubs, there will need to be multiple IOMMUs as well.
Existing AMD64 devices already include a more limited address translation facility, called a GART (Graphics Address Remapping Table), right on chip. The on-chip GART has been used for device address translation in existing systems, and is sometimes itself referred to as an IOMMU (especially in discussions of the Linux kernel), which can lead to confusion between the existing GART and the new IOMMU specification that we're discussing here.
The GART was originally designed to allow graphics chips to read textures directly from system memory, using address translation to gather allocations in system memory into a contiguous region mapped to an address that the graphics device could see. But the GART has also been put to use by Linux kernel programmers to enable legacy 32-bit PCI devices to access regions of system memory outside of their addressable range. This is done by programming the device to work inside the "graphics aperture" memory region controlled by the GART, and then using the GART to translate this address to the real target address, above 4 GB.
The new IOMMU can do this trick, too, only without the restrictions of the GART (which, after all, wasn't designed for this purpose). While the GART is limited to working inside the graphics aperture, the IOMMU can translate any address presented by the device to a system address.
More important, the IOMMU provides protection mechanisms that restrict device access to memory, whereas the GART performs translation only. It's the combination of address translation and access protection that makes the IOMMU so valuable for virtualization.
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Perhaps GART IOMMU was finaly depreciated ? Or the appearence of the option relies on some other config option set (I would assume AGP related) |
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lxg
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Joined: 12 Nov 2005
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| Posted: Tue Jul 13, 2010 9:40 pm Post subject: |
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| Code: |
.config - Linux Kernel v2.6.34-gentoo-r1 Configuration
──────────────────────────────────────────────────────────────────────────────
┌──────────────────────────── Search Results ─────────────────────────────┐
│ Symbol: GART_IOMMU [=y] │
│ Prompt: GART IOMMU support │
│ Defined at arch/x86/Kconfig:661 │
│ Depends on: X86_64 [=y] && PCI [=y] && K8_NB [=y] && EMBEDDED [=n] │
│ Location: │
│ -> Processor type and features │
│ Selects: SWIOTLB [=y] │
│ │
│ │
│ │
│ │
│ │
│ │
│ │
├─────────────────────────────────────────────────────────────────(100%)──┤
│ < Exit > │
└─────────────────────────────────────────────────────────────────────────┘
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Pressing / in the kernel's menuconfig lets you search for strings in option names.
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aCOSwt
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| Posted: Tue Jul 13, 2010 10:09 pm Post subject: |
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| lxg wrote: | | Depends on: X86_64 [=y] && PCI [=y] && K8_NB [=y] && EMBEDDED [=n] |
All right then, it now depends on K8_NB (which was not the case in earlier kernel versions)
Which means that it will only operate in case of a K8 Northbridge.
What about the "software bounce buffer based IOMMU used on Intel systems as fallback" ?
Great thanks for your finding lxg. As well as for your suggestion I new nothing about despite being a vi fanatic... |
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lxg
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| Posted: Tue Jul 13, 2010 11:16 pm Post subject: |
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You're welcome. 
| aCOSwt wrote: | | What about the "software bounce buffer based IOMMU used on Intel systems as fallback" ? |
Um, what do you mean with what about…? This text is in the description of the GART_IOMMU option. Your question indicates that this is supposed to be another option, but this is not the case.
| Code: | CONFIG_GART_IOMMU:
Support for full DMA access of devices with 32bit memory access only
on systems with more than 3GB. This is usually needed for USB,
sound, many IDE/SATA chipsets and some other devices.
Provides a driver for the AMD Athlon64/Opteron/Turion/Sempron GART
based hardware IOMMU and a software bounce buffer based IOMMU used
on Intel systems and as fallback.
The code is only active when needed (enough memory and limited
device) unless CONFIG_IOMMU_DEBUG or iommu=force is specified
too. |
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s4e8
Guru
Joined: 29 Jul 2006
Posts: 311
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| Posted: Wed Jul 14, 2010 1:51 am Post subject: |
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You need GART_IOMMU, because it select the SWIOTLB.
SWIOTLB is forced since v2.6.29, so you needn't GART_IOMMU anymore except you have the real hardware component. |
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aCOSwt
Bodhisattva
Joined: 19 Oct 2007
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Location: Hilbert space
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| Posted: Wed Jul 14, 2010 4:12 pm Post subject: |
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| lxg wrote: | | Um, what do you mean with what about…? |
I meant that as I have no dedicated hardware acting as IOMMU (K8 northbridge for example), I thought that GART_IOMMU was the mean for my intel system to emulate this function.
In other words, where has the emulation gone ?
| s4e8 wrote: | | You need GART_IOMMU, because it select the SWIOTLB. |
As a matter of fact, Exactly !
Thanks s4e8 for pointing this out
2.6.33 : GART_IOMMU [=y] && X86_64 [=y] && PCI [=y] => SWIOTLB
So I was obliged to select GART_IOMMU in order to get SWIOTLB on earlier versions.
2.6.34 : GART_IOMMU [=n] && X86_64 [=y] && PCI [=y] && K8_NB [=n] => SWIOTLB
And by now, SWIOTLB will be active if I get no dedicated hardware and GART_IOMMU unset !
Grrreat ! I am happy ! Thank you all for being responsible for this !  |
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