brendlefly62
Apprentice
Joined: 19 Dec 2009
Posts: 150
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 Posted: Thu Jul 18, 2024 10:33 pm Post subject: Cross-building kernels w make prepare make oldconfig |
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Hi there, kernel-builders! Can someone confirm or correct my "understanding"  of the importance of "make prepare" in this scenario?
I've been using the procedure below to cross-build kernel updates for multiple target architectures. It is based on instructions I found in discussions I ran across in research I did a couple of years ago, and some trial-and-error. I use the same script to cross-build kernels for several different target architectures (several different "build" directories on the same workhorse AMD64 host). Rather than exporting multiple varaibles, I use a single bash variable to consolidate the make command for simpler cli operation, like --
make_me="make O=${model_dir}/ ARCH=${arch} CROSS_COMPILE=${cross_compile} "
My sequence uses "make oldconfig" as I've been accustomed to for years, but it also employs "make prepare" (the instructions on which I based the procedure used "make prepare" prior to "make oldconfig", but I have since switched the order, and it still seems to work). I had never used "make prepare" until I saw it referenced in those instructions for cross-building multiple target architectures...
The sequence (outlined below) works, but I don't fully understand the need for "make prepare" and its order relative to "make oldconfig" -- is make prepare really necessary? (is that because I'm using O= ?). I've seen that whichever I run first, "make prepare" or "make oldconfig" is often interactive - answer new questions to migrate the old .config to the new version (which is what I expected from oldconfig but was surprised to see when prepare is made first) -- when running "make prepare" and then "make oldconfig" there is no interactive Q&A for "make oldconfig" - it seems to only build a new Makefile in the O= build directory. I now run "make oldconfig" followed by "make prepare" and now "make oldconfig" is interactive Q&A (as expected) and make prepare has several lines of "CC xxxxx" output
Here is an outline of my cross-build sequence -
| Code: | # get new sources in $sources_dir
cd $sources_dir
make_me mrproper #(if re-building)
# copy target's running .config to $sources_dir
make_me oldconfig
make_me prepare
make_me menuconfig
cp .config to save new config
make_me ### (build all targets with "*" in make help outline)
# then I make install, modules_install, dtbs_install, to stage the kernel, modules, and dtbs so I can build a tarball, and then deploy the tarball to the target system |
Can someone confirm or clarify for me? --
In a sources directory, "make help" does not describe a "prepare" target...
| Code: | # make help | grep prepare
modules_prepare - Set up for building external modules |
The need for "make prepare" seems to have something to do with the fact that I'm building in O= and the make process runs recursively in several directories, so some modifications are made before descending recursively ... I see in the 6.9.9 Makefile, these explanatory comments "
# The only cases where we need to modify files which have global
# effects are thus separated out and done before the recursive
# descending is started. They are now explicitly listed as the
# prepare rule."
and
# Things we need to do before we recursively start building the kernel
# or the modules are listed in "prepare".
# A multi level approach is used. prepareN is processed before prepareN-1.
# archprepare is used in arch Makefiles and when processed asm symlink,
# version.h and scripts_basic is processed / created.
I also see an error message related to invalid kernel configuration -
"...
echo >&2 " ERROR: Kernel configuration is invalid."; \
echo >&2 " include/generated/autoconf.h or $@ are missing.";\
echo >&2 " Run 'make oldconfig && make prepare' on kernel src to fix it."; \
..."
But that is the only "official" place I've seen advice to run "make prepare" |
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