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mattjgalloway
l33t
Joined: 16 Mar 2004
Posts: 761
Location: Coventry, UK
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 Posted: Sun Nov 27, 2005 6:12 pm Post subject: AMD64 Cache Layout |
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Hey guys,
I know this isn't strictly a Gentoo related problem, but it's AMD64 related and I know I'll get more responses here. But if a mod wants to move it to Off The Wall then go for it.
Anyway.... basically I have a report to do for my computer architecture course and we've been given a program which can help work out the cache layout a CPU has. I've run it through a cache simulator we've got and I think I know how it works. (The code is at the bottom for anyone interested).
But what I need to know is, does anyone know the actual layout of an AMD64 CPU? That's what I'm running on and if I could find out for definate then I could compare in my report the layout I found to what is actually in the hardware - obviously my numbers might come out slightly wrong due to other processes running, etc. Also, layouts of other CPUs might be handy... I just need to know size, block size, associativity and replacement algorithm.
Your help is appreciated!!!
Code to detect cache structure:
| Code: | const int listSize = 1000000; // try different list sizes
int l[listSize];
int main()
{
int i, j, k, stride, repetitions;
stride = 1; // try different strides
repetitions = 10; // access the same data many times
for (i=0; i < repetitions; i++) {
for(j=0; j < listSize; j+= stride) {
k = l[j];
}
}
return 0;
} |
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AMD64 3200+, 1024MB RAM, Gentoo Linux
MacBook Core Duo, 1024MB RAM, Leopard |
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NeddySeagoon
Administrator
Joined: 05 Jul 2003
Posts: 54420
Location: 56N 3W
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| Posted: Sun Nov 27, 2005 7:11 pm Post subject: |
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mattjgalloway,
The [http://www.amd.com/us-en/Processors/TechnicalResources/0,,30_182_739_9003,00.html]data sheet [/uml]tells you what you want to know. For the Opteron its
64kB 2-Way Associative ECC-Protected L1 Data Cache
64kB 2-Way Associative Parity Protected L1 Instruction Cache
1MB 16-Way Associative ECC-Protected L2 Cache
Further, the L1 and L2 caches are exclusive. An item can be in one or the other but not both.
Edit---
I didn't check the cache line size. Its either 64 bytes or 128 bytes
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Regards,
NeddySeagoon
Computer users fall into two groups:-
those that do backups
those that have never had a hard drive fail. |
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Gnufsh
Guru
Joined: 28 Dec 2002
Posts: 400
Location: Portland, OR
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| Posted: Sun Nov 27, 2005 10:28 pm Post subject: |
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sandpile.org is a good place to look for this information:
| Code: |
Processor Caches Level 0 N/A
Level 1 Code 64 KB, 2-Way, 64 Byte/Line, SI, LRU,
Pre-decode and Branch Information, Parity
Data 64 KB, 2-Way, 64 Byte/Line, MOESI, LRU,
Dual-ported, WB, WA, 8 Banks, ECC
Level 2 Unified (Model 5)
On-Die 1,024 KB, 16-Way, 64 Byte/Line, Pseudo-LRU,
Exclusive, ECC (is used for Parity, Pre-decode,
and Branch Information if L2 Line holds Code)
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This review aslo has good information:
http://www.cpuid.com/reviews/K8/index.php
The cache line size is 64 bytes. |
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mattjgalloway
l33t
Joined: 16 Mar 2004
Posts: 761
Location: Coventry, UK
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| Posted: Mon Nov 28, 2005 12:18 pm Post subject: |
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Cheers guys, I've checked both those sites out and both very helpful! Cheers!
My report will look extra special now!
Many thanks.
(If anyone else has any comments on any commonly used cache system then I'd be more than happy to hear about it)
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MacBook Core Duo, 1024MB RAM, Leopard |
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