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Master One
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 Posted: Mon Jul 03, 2006 9:40 pm Post subject: Need advice: Dual Xeon EM64T w/ different models & stepp |
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I recently bought a second (used) Xeon EM64T CPU for my IBM eServer xSeries 226 on ebay. I used the IBM FRU number to search for the item, and I was pretty sure, I'd get an identical unit to the first processor. I just installed this second CPU today, and it turned out to be a different model & stepping. At first the post bios message told me, that my second CPU is installed incorrectly, and that I have to move CPU0 to socket1 & CPU1 to socket0, to have it working correctly (what I did, and the message didn't show up any more). Other CPU matters, that can be accessed in the bios menu look normally, except the model and stepping info, and that the freshly bought Xeon processor shows a temperature of about 62°C, while the CPU that came with my eServer shows only about 42°C.
Of course I have Gentoo Linux installed on that machine. It boots normally with the second CPU installed (it's a x86_64 nocona installation, and I just had to adjust the numbers of CPUs in the kernel config), and dmesg shows nothing abnormal, except an APIC error 00(40) on all 4 found CPUs (no idea what that means, maybe my server needs a firmware update?). Now comes the interesting part, the output of /proc/cpuinfo: | Code: | processor : 0
vendor_id : GenuineIntel
cpu family : 15
model : 3
model name : Intel(R) Xeon(TM) CPU 3.20GHz
stepping : 4
cpu MHz : 3200.250
cache size : 1024 KB
physical id : 0
siblings : 2
core id : 0
cpu cores : 1
fpu : yes
fpu_exception : yes
cpuid level : 5
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm constant_tsc pni monitor ds_cpl cid xtpr
bogomips : 6406.49
clflush size : 64
cache_alignment : 128
address sizes : 36 bits physical, 48 bits virtual
power management:
processor : 1
vendor_id : GenuineIntel
cpu family : 15
model : 4
model name : Intel(R) Xeon(TM) CPU 3.20GHz
stepping : 1
cpu MHz : 3200.250
cache size : 1024 KB
physical id : 3
siblings : 2
core id : 3
cpu cores : 1
fpu : yes
fpu_exception : yes
cpuid level : 5
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall nx lm constant_tsc pni monitor ds_cpl cid cx16 xtpr
bogomips : 6399.38
clflush size : 64
cache_alignment : 128
address sizes : 36 bits physical, 48 bits virtual
power management:
processor : 2
vendor_id : GenuineIntel
cpu family : 15
model : 3
model name : Intel(R) Xeon(TM) CPU 3.20GHz
stepping : 4
cpu MHz : 3200.250
cache size : 1024 KB
physical id : 0
siblings : 2
core id : 0
cpu cores : 1
fpu : yes
fpu_exception : yes
cpuid level : 5
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm constant_tsc pni monitor ds_cpl cid xtpr
bogomips : 6399.38
clflush size : 64
cache_alignment : 128
address sizes : 36 bits physical, 48 bits virtual
power management:
processor : 3
vendor_id : GenuineIntel
cpu family : 15
model : 4
model name : Intel(R) Xeon(TM) CPU 3.20GHz
stepping : 1
cpu MHz : 3200.250
cache size : 1024 KB
physical id : 3
siblings : 2
core id : 3
cpu cores : 1
fpu : yes
fpu_exception : yes
cpuid level : 5
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall nx lm constant_tsc pni monitor ds_cpl cid cx16 xtpr
bogomips : 6399.40
clflush size : 64
cache_alignment : 128
address sizes : 36 bits physical, 48 bits virtual
power management: |
As you can see, the two CPUs mainly differ on two flags: nx & cx16 (so these two are missing on the CPU I recently bought second hand on ebay).
This leaves me with the following questions:
1. What are those two CPU flags all about?
2. Is there any disadvantage to use those two CPUs together?
3. Is there a way to check, if the recently bought second CPU is even an EM64T one (should be, but how to be sure)?
4. Is the mentioned APIC error on all 4 CPUs a real problem?
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Master One
l33t
Joined: 25 Aug 2003
Posts: 754
Location: Austria
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| Posted: Tue Jul 04, 2006 12:05 pm Post subject: |
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Ok, in the meantime I did some more digging.
I just found out that the LM (= Long Mode) flag is the indicator for the EM64T extension, so both of my CPUs are indeed noconas.
The cx16 flag tells "This processor supports the CMPXCHG16B instruction" (compare & exchange 16 byte), but still no idea, what that means, and if this is a problem, if one of the two CPUs supports that flag, and the other not.
Concerning the nx flag I assume this must be the "No Execution" feature. I really don't know how it is possible, that that flag is missing on one of the two CPUs, because I thought this feature is implemented in all Xeons. Again no idea, if that's a problem, if used together with the second CPU which supports that flag.
I really would appreciate some input on these concerns.
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mbar
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Master One
l33t
Joined: 25 Aug 2003
Posts: 754
Location: Austria
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| Posted: Sun Jul 09, 2006 4:10 pm Post subject: |
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Thanks for the hint, mbar, but that didn't really help. There are no relevant bios options concerning the processors, they are detected automatically.
More digging revealed, that I simply bought the wrong processor, although I really don't understand, how this is even possible.
The CPU that came with my eServer has the SSpec SL7PF, and the CPU I bought on ebay has SL7DX. They both seem to be identical (really could not find any difference between the two on the net, even comprehensive Xeon comparison tables like this one do not show any differences), but they are not, as seen from the /proc/cpuinfo output.
I still have no idea, if I now should buy another SL7PF, or if I can use the SL7DX together with the SL7PF in my eServer without any problems or disadvantages.
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mbar
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| Posted: Sun Jul 09, 2006 5:31 pm Post subject: |
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Try to find a Xeon datasheet on www.intel.com This datasheed should have all the info on the various steppings. Check the "errata" section and find any differences. Intel is known to make a few revisions of each chip, even for the same stepping. Datasheets are public, you don't need to register or sth (I had my own Pentium 4 era once  ).
EDIT: http://www.intel.com/design/Xeon/documentation.htm
ERRATA http://www.intel.com/design/xeon/specupdt/302402.htm
See errata on page 13, you have processors with cpuid 0F34h and 0F41h
MORE EDIT
Seems that 0F34 has a lot more bugs, including this one
S55 X Fixed CPUID instruction incorrectly reports CMPXCH16B as
supported |
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Master One
l33t
Joined: 25 Aug 2003
Posts: 754
Location: Austria
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| Posted: Sun Jul 09, 2006 8:08 pm Post subject: |
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Thanks again, that document was helpful. I'm not quite sure how this errata are exactly meant to be understood, because if it tells: | Code: | | X: Erratum, Specification Change or Clarification that applies to the given processor stepping |
and | Code: | | Fixed: This erratum has been previously fixed |
Does that mean, it's fixed for that stepping, or has it been fixed for the next stepping?
If it's fixed for the given stepping, 0F34h would not have more bugs than 0F41h, because mostly when it tells "X" it also tells "Fixed".
The interesting part in this document is page 10 & 11, where it tell, if and how mixed steppings can be used in a DP system. As it turns out, 0F34h & 0F41h can be used in the same machine without problems ("Currently no known issues associated with mixing these steppings"), and | Code: | In mixed stepping systems, the processor with the lowest feature-set, as determined by the
CPUID Feature Bytes, must be the Bootstrap Processor (BSP). In the event of a tie in
feature-set, the tie should be resolved by selecting the BSP as the processor with the lowest
stepping as determined by the CPUID instruction. |
explains, why I had to move my CPU SL7PF to socket 1, and insert CPU SL7DX into socket 0.
The notes on page 9 confirm, that SL7DX is missing "Enhanced Halt State (C1E)" and "Execute Disable bit functionality".
So the big question still remains:
How will the system perform with these two CPUs, as CPU0 is missing the flags "nx" & "cx16"?
I really do not understand, how this should work out, because although the flags "nx" & "cx16" are showing up in /proc/cpuinfo for CPU1 (SL7PF), one has to assume that they are not useable, because the bootstrap processor (SL7DX) does not support them.
So I am still unsure, if I should try to sell CPU SL7DX again, and purchase a second SL7PF, or if I can stick with these two different steppings with my mind at rest.
Any further input is highly appreciated.
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mbar
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| Posted: Sun Jul 09, 2006 8:28 pm Post subject: |
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For this X / Fixed mess I think that X means 'bug present' and is fixed in these steppins that do not have X in the table.
Now I can only speculate, but I think that system will use 'lowest common denominator', and not use features not present in the bootstrap processor. But pls have a second opinion on that 
I would sell older processor (0F34) and buy newer (0F41).
EDIT And it might be that XD bit is not functional in CPUID flags, but the processor has it working (only its not reported). |
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Master One
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| Posted: Sun Jul 09, 2006 8:43 pm Post subject: |
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| mbar wrote: | | For this X / Fixed mess I think that X means 'bug present' and is fixed in these steppins that do not have X in the table. |
Don't thing so, because of "(No mark) or (Blank Box): This erratum is fixed in listed stepping or specification change does not apply to listed stepping." But on the other hand it would stay a miracle, where it got fixed then. That's pretty badly explained in that document.
| mbar wrote: | | Now I can only speculate, but I think that system will use 'lowest common denominator', and not use features not present in the bootstrap processor. But pls have a second opinion on that |
That's what I think as well, because how could tasks be spread among these two processors, if one has two more features, if not stripped down to the lowest common featureset.
| mbar wrote: | | I would sell older processor (0F34) and buy newer (0F41). |
I am thinking about going that way, unfortunately I seem to have bought this SL7DX at a too high price (including the IBM heatsink for my eServer and P&P it was about 180,- EURO), and it will be hard to sell without huge loss. I really should have informed myself better before taking that bid, but I was so sure that it's gonna be alright going after the IBM FRU, which was a pretty damned mistake, for which I could kick my own butt now... 
| mbar wrote: | | EDIT And it might be that XD bit is not functional in CPUID flags, but the processor has it working (only its not reported). |
Don't think so, because then SL7DX would have got note (6) at page 8. Note (6) tells "These parts have Execute Disable bit functionality", and all listed CPUs after the first 10 S-Specs have got that note (and SL7DX is among those first 10 S-Specs).
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mbar
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| Posted: Sun Jul 09, 2006 8:55 pm Post subject: |
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| One thing that strikes me the most is that wikipedia and that Xeon comparison page is utterly wrong about core steppings and XD bit capability. |
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Master One
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| Posted: Sun Jul 09, 2006 11:22 pm Post subject: |
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Yep, one never stops learning something new...
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